The present invention relates to a method of manufacturing semiconductor devices, e.g., MOS-type transistors and integrated circuits comprising such devices, with improved processing methodology resulting in increased quality, e.g., lower junction-to-substrate capacitance, and MOS-type devices obtained thereby. The present invention is also useful in the manufacture of CMOS semiconductor devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 um, e.g., about 0.15 um and below.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor devices require design features of 0.18 um and below, such as 0.15 um and below, increased transistor and circuit speeds, high reliability and quality, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 um and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices are reduced into the sub-micron range, so-called xe2x80x9cshort channelxe2x80x9d effects arise which tend to limit device performance. For n-channel transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem is attributed to high electrical fields between the source and the drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, lightly-doped source/drain extension structures have been developed.
For p-channel transistors of short-channel type, the major limitation on performance arises from xe2x80x9cpunch-throughxe2x80x9d effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned xe2x80x9cpunch throughxe2x80x9d current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped drain region is laterally displaced away from the gate by the use of a sidewall spacer on the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
A further problem or drawback encountered with the manufacture of such submicron-dimensioned MOS-type transistor devices, which problem is not addressed or ameliorated by the above-described formation of lightly- or moderately-doped source/drain extensions, arises from source/drain junction-to-substrate capacitance effects. More specifically, high source/drain junction-to-substrate capacitance adversely affects, i.e., degrades, transistor performance characteristics. However, the parallel trends towards increased microminiaturization and large scale integration require MOS and MOS-type transistor devices with reduced source/drain junction-to-substrate capacitance, for meeting overall device performance requirements.
Thus, a need exists for improved semiconductor manufacturing methodology for fabricating MOS and CMOS transistors, which methodology substantially reduces or eliminates the deleterious effects on device performance attributed to high source/drain-to-junction capacitance effects. Moreover, there exists a need for an improved process for fabricating MOS transistor-based devices which is fully compatible with conventional process flow and requirements for manufacturing throughput and product yield.
An advantage of the present invention is an improved method for forming semiconductor junctions with substantially reduced junction-to-semiconductor substrate capacitance.
Another advantage of the present invention is an improved method for manufacturing MOS and/or CMOS transistor devices with substantially reduced source/drain junction-to-substrate capacitance.
Yet another advantage of the present invention is an improved silicon-based MOS-type transistor device having substantially reduced source/drain junction-to-substrate capacitance.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device having reduced junction-to-substrate capacitance, which method comprises the sequential steps of:
(a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type having a surface;
(b) selectively introducing dopant impurities of a second conductivity type opposite the first conductivity type into at least one portion of said substrate, for forming at least one semiconductor junction at a preselected ultimate depth below the substrate surface;
(c) selectively introducing oxygen atoms and/or molecules into the at least one portion of the substrate, such that a peak concentration of the oxygen atoms and/or molecules occurs just below the ultimate depth of the at least one semiconductor junction; and
(d) thermally treating the oxygen-introduced substrate at a temperature and for an interval sufficient to effect reaction between the semiconductor substrate and the introduced oxygen atoms and/or molecules, thereby forming an oxide barrier in the substrate just below the ultimate depth of the at least one semiconductor junction, thereby reducing junction-to-substrate capacitance.
In embodiments according to the present invention, step (a) comprises providing a silicon wafer substrate and step (d) comprises rapid thermal annealing (RTA) at a temperature of from about 1,000-1,050xc2x0 C. for about 10-15 seconds.
In further embodiments according to the present invention, step (a) comprises providing a device precursor structure comprising a layer stack formed on a portion of the substrate surface, the layer stack comprising:
i. a thin gate insulating layer in contact with the substrate surface; and
ii. a gate electrode layer formed on the gate insulating layer, the layer stack comprising a pair of opposing side surfaces and a top surface, with a sidewall spacer of an insulative material formed on each of the opposing side surfaces; and
step (b) comprises introducing the dopant impurities of second conductivity type, opposite the first conductivity type, into portions of the substrate adjacent each of the sidewall spacers, thereby forming source/drain regions in the substrate; the device precursor structure comprises a silicon wafer substrate, the thin gate insulating layer comprises a silicon oxide layer about 25-50 Angstroms thick, the gate electrode layer comprises heavily-doped polysilicon, the sidewall spacers each comprise an oxide, nitride, or oxynitride of silicon; and the method further comprises step (e) of forming, as by a salicide process, ohmic-electrical contacts to the top surface of the gate electrode layer and to each of the source/drain regions.
In yet further embodiments according to the invention, step (b) comprises implanting the second, opposite conductivity type dopant impurities at a preselected dosage and energy for providing the at least one semiconductor junction at the preselected depth below the substrate surface; step (c) comprises implanting the oxygen atoms and/or molecules at a preselected dosage and energy for providing the peak concentration of oxygen atoms and/or molecules just below the ultimate depth (i.e., after thermal annealing) of the at least one semiconductor junction; and the method comprises the further step (e) of forming an ohmic electrical contact to the at least one semiconductor junction.
According to another aspect of the present invention, a method of manufacturing a silicon-based MOS-type transistor device having reduced source/drain junction-to-semiconductor substrate capacitance comprises the sequential steps of:
(a) providing a MOS transistor precursor structure comprising a silicon wafer substrate of a first conductivity type and a layer stack formed on a portion of the surface of the wafer substrate, the layer stack comprising:
i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 Angstroms thick in contact with the wafer surface; and
ii. a gate electrode layer comprising heavily-doped polysilicon formed on the gate insulating layer, the layer stack comprising a pair of opposing side surfaces and a top surface, with an insulative sidewall spacer comprising an oxide, nitride, or oxynitride of silicon formed on each of the opposing side surfaces of the layer stack,
(b) selectively implanting dopant impurities of second, opposite conductivity type into portions of the substrate adjacent the sidewall spacers for forming spaced-apart source/drain junction regions in the substrate, the dosage and energy of the implanted dopant impurities being selected for providing source/drain junctions at a preselected depth below the wafer substrate surface;
(c) selectively implanting oxygen atoms and/or molecules into the wafer substrate portions adjacent the sidewall spacers, the implanted oxygen atoms and/or molecules having a dosage and energy selected for providing a peak concentration of implanted oxygen atoms and/or molecules just below the ultimate depth of the source/drain junctions;
(d) thermally treating the oxygen-implanted substrate at a temperature of about 1,000-1,050xc2x0 C. for about 10-15 seconds for effecting reaction between the silicon wafer substrate and the implanted oxygen atoms and/or molecules, thereby forming a silicon oxide barrier in the substrate just below each of the source/drain junctions; and
(e) forming electrically conductive refractory metal silicide ohmic metal contacts to the top surface of the gate electrode layer and to the source/drain junction regions by a salicide process.
In embodiments according to the present invention, step (a) comprises providing an n-type silicon wafer substrate; step (b) comprises implanting boron-containing p-type dopant impurities at preselected dosages and energies for forming source and drain junctions at a desired ultimate depth below the wafer substrate surface; and step (c) comprises implanting oxygen atoms and/or molecules at preselected dosages and energies for providing a peak concentration of implanted oxygen atoms and/or molecules at a preselected depth below the substrate surface.
In other embodiments according to the present invention, step (a) comprises providing a p-type silicon wafer substrate; step (b) comprises implanting phosphorus- or arsenic-containing n-type impurities at preselected dosages and energies for forming source and drain junctions at a desired ultimate depth below the wafer substrate surface; and step (c) comprises implanting oxygen atoms and/or molecules at preselected dosages and energies for providing the peak concentration of implanted oxygen atoms and/or molecules at a preselected depth below the substrate surface.
In further embodiments of the present invention, step (e) comprises forming an electrically conductive metal silicide of a refractory metal selected from the group consisting of titanium, nickel, and cobalt.
According to still another aspect of the present invention, a silicon-based MOS transistor having reduced source/drain junction-to-substrate capacitance comprises:
a silicon semiconductor wafer substrate of a first conductivity type and having a surface;
a layer stack formed on a portion of the wafer surface, the layer stack comprising:
i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 Angstroms thick in contact with the portion of the wafer surface; and
ii. a gate electrode layer comprising heavily-doped polysilicon formed on the gate insulating layer, the layer stack comprising a pair of opposing side surfaces and a top surface, with an insulative sidewall spacer comprising an oxide, nitride, or oxynitride of silicon formed on each of the opposing side surfaces;
source/drain junction regions of preselected depth below the wafer surface formed in portions of the wafer substrate adjacent the sidewall spacers;
a silicon oxide barrier layer selectively formed within the wafer substrate just below each of the source and drain junction regions for reducing source/drain junction-to-substrate capacitance; and
electrically conductive refractory metal silicide ohmic contacts formed on the top surface of the gate electrode and on each of the source and drain junction regions.
In embodiments according to the present invention, the silicon wafer substrate is n-type and the source/drain junction regions are p-type; whereas, in other embodiments according to the present invention, the silicon wafer substrate is p-type and the source/drain junction regions are n-type.
In further embodiments according to the present invention, the electrically conductive metal silicide of the ohmic contacts comprises a refractory metal selected from the group consisting of titanium, nickel, and cobalt; and the MOS device has a substantially reduced source/drain junction-to-substrate capacitance.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.